essai Debug.cfg 670 B

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  1. # This is an essai board with a single STM32F401RCTx chip
  2. #
  3. # Generated by System Workbench for STM32
  4. # Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s)
  5. source [find interface/stlink.cfg]
  6. set WORKAREASIZE 0x8000
  7. transport select "hla_swd"
  8. set CHIPNAME STM32F401RCTx
  9. # Enable debug when in low power modes
  10. set ENABLE_LOW_POWER 1
  11. # Stop Watchdog counters when halt
  12. set STOP_WATCHDOG 1
  13. # STlink Debug clock frequency
  14. set CLOCK_FREQ 4000
  15. # use software system reset
  16. reset_config none
  17. set CONNECT_UNDER_RESET 0
  18. source [find target/stm32f4x.cfg]